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e preliminary october 1996 order number: 290578-003 n high performance read ? 80/120 ns max access time 40 ns max. output enable time n low power consumption ? 20 ma typical read current n x8-only input/output architecture ? space-constrained 8-bit applications n optimized array blocking architecture ? one 16-kb protected boot block ? two 8-kb parameter blocks ? one 96-kb main block ? one 128-kb main block ? top boot location n hardware data protection feature ? erase/write lockout during power transitions ? absolute hardware protection for boot block n software eeprom emulation with parameter blocks n extended cycling capability ? 100,000 block erase cycles n automated byte write and block erase n industry-standard command user interface ? status registers ? erase suspend capability n sram-compatible write interface n reset/deep power-down input ? 0.2 a i cc typical ? provides reset for boot operations n industry-standard surface mount packaging ? 40-lead tsop ? 44-lead psop ? 40-lead pdip n etox? iv flash technology ? 5v read n 12v write and block erase ? v pp = 12v 5% standard ? v pp = 12v 10% option n independent software vendor support intels 2-mbit flash memory is an extension of the boot block architecture which includes block-selective erasure, automated write and erase operations, and a standard microprocessor interface. the 2-mbit flash memory enhances the boot block architecture by adding more density and blo cks, x8 i nput/output control, very high-speed, low-power, and industry-standard rom-compatible pinout and surface mount packaging. the intel 28f002bc is an 8-bit wide flash memory offering. this high-density flash memory provides user- selectable bus operation for 8-bit applications. the 28f002bc is a 2,097,152-bit nonvolatile memory organized as 262,144 bytes of information. it is offered in 44-lead psop, 40- lead pdip and 40-lead tsop package, which is ideal for space-constrained portable systems or any application with board space limitations. this device uses an integrated command user interface (cui) and write state machine (wsm) for simplified byte write and block erasure. the 28f002bc provides block locations compatible with intels mcs?-186 family, 80286, 90860ca, and the intel386?, intel486?, pentium?, and pentium pro microprocessors. the boot block includes a data protection feature to protect the boot code in critical applications. with a maximum access time of 80 ns, this high-performance 2-mbit flash memory interfaces at zero wait-state to a wide range of microprocessors and microcontrollers. a deep power-down mode lowers the total v cc power consumption to 1 w typical. this power savings is critical in hand-held battery powered systems. for very low-power applications using a 3.3v supply, refer to the intel 28f002bv-t/b 2-mbit smartvoltage boot block flash memory datasheet. manufactured on intels 0.6 micron etox? iv process technology, the 28f002bc flash memory provides world-class quality, reliability, and cost-effectiveness at the 2-mbit density. 28f002bc 2-mbit (256k x 8) boot block flash memory
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f002bc may contain design defects or errors known as errata. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 copyright ? intel corporation, 1996 cg-041493
e 28f002bc 2-mbit boot block flash memory 3 preliminary contents page page 1.0 introduction .............................................5 1.1 designing for density upgradeability............5 1.2 main features ..............................................5 1.3 applications..................................................6 1.4 pinouts.........................................................7 1.5 pin descriptions .........................................10 2.0 product description............................11 2.1 memory organization.................................12 2.1.1 blocking...............................................12 2.1.2 28f002bc-t block memory map.........12 3.0 principles of operation .....................12 3.1 bus operations ..........................................13 3.2 read operations ........................................13 3.2.1 read array ..........................................13 3.2.2 intelligent identifiers ............................14 3.3 write operations ........................................14 3.3.1 command user interface (cui) ...........14 3.3.2 status register....................................17 3.3.3 program mode.....................................17 3.3.4 erase mode .........................................18 3.3.5 extended cycling ................................19 3.4 boot block locking.....................................19 3.4.1 v pp = v il for complete protection........19 3.4.2 rp# = v hh for boot block unlocking....19 3.5 power consumption ...................................23 3.5.1 active power .......................................23 3.5.2 standby power ....................................23 3.5.3 deep power-down...............................23 3.6 power-up/down operation.........................23 3.6.1 rp# connected to system reset ........23 3.6.2 v cc , v pp and rp# transitions .............23 3.7 power supply decoupling ..........................24 3.7.1 v pp trace on printed circuit boards ....24 4.0 electrical specifications..................25 4.1 absolute maximum ratings........................25 4.2 operating conditions..................................25 4.2.1 capacitance.........................................26 4.2.2 input/output test conditions ...............26 4.2.3 dc characteristics...............................27 4.2.4 ac characteristics ...............................29 appendix a: ordering information .................35 appendix b:wsm transition table.................36 appendix c: additional information ...............37
28f002bc 2-mbit boot block flash memory e 4 preliminary revision history number item -001 original version -002 pin 2 of 44-lead psop changed from du to nc alternate program command (10h) removed wsm transition table added -003 40-lead pdip package added
e 28f002bc 2-mbit boot block flash memory 5 preliminary 1.0 introduction this datasheet comprises the specifications for the 28f002bc 2-mbit flash memory. section 1 provides an overview of the 2-mbit flash memory, including applications, pinouts, and pin descriptions. section 2 describes the memory organization in detail. section 3 defines a description of the memorys principles of operation. finally, section 4 details the memorys operating specifications. 1.1 designing for density upgradeability the 28f002bc has been optimized to meet market requirements. applications currently using the 28f001bx and 28f002bx can migrate to this product. of course, both the 28f001bx and the 28f002bx devices use an 8-bit wide bus. those applications needing a 16-bit wide bus or lower voltage can convert to the smart 5 or smartvoltage family of flash memory products. smartvoltage is also the natural migration path to the 4-mbit density. both the 28f002bc and the 4-mbit smartvoltage are offered in identical packages to make upgrade seamless. a few simple considerations can smooth the migration path significantly: 1. connect the nc pin of the 28f002bc to gnd (this will retain boot block locking when a 4-mbit smartvoltage is inserted). 2. design a switchable v pp to take advantage of the 5v v pp option on smartvoltage devices. 3. if anticipating to use the 5v v pp option, switch v pp to gnd for complete write protection. previous designs with intels 28f002bx devices on occasion had to use a nor gate (or some other scheme) to prevent issues with floating addresses latching incorrect data. the 28f002bc has corrected this issue and does not need the nor gate. when migrating a design using the 28f002bx to the 28f002bc, the nor gate can be removed. when considering upgrading, packaging is of paramount importance. current and future market trends indicate tsop and psop as the packages that will enable designs into the next century. 1.2 main features the 28f002bc boot block flash memory is a high- performance, 2-mbit (2,097,152 bit) flash memory organized as 256 kbytes (262,144 bytes) of 8 bits each. the 28f002bc has separately erasable blo cks, including a hardware-lockable boot block (16,384 bytes), two parameter blocks (8, 192 bytes each) and two main blo cks ( one block of 98,304 bytes and one block of 131,072 bytes). an erase operation typically erases one of the main blocks in 2.4 seconds and the boot or parameter blo cks in 1.0 second. each block can be independently erased and programmed 100,000 times. the boot block is located at the top of the address map to match the protocol of many systems, including intels mcs-186 family, 80960ca, i860? microprocessors as well as pentium and pentium pro microprocessors. the hardware-lockable boot block provides the most secure code storage. the boot block is intended to store the kernel code required for booting-up a system. when the rp# pin is between 11.4v and 12.6v, the boot block is unlocked and program and erase operations can be performed. when the rp# pin is at or below 6.5v, the boot block is locked and program and erase operations to the boot block are ignored. the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the 28f002bc. program and erase automation allows program and erase operations to be executed using an industry standard two-write command sequence to the cui. data writes are performed in byte increments. each byte in the flash memory can be programmed independently of other memory locations but is erased simultaneously with all other locations within the block. the status register (sr) indicates the status of the internal write state machine (wsm), which reports critical information on program and/or erase sequences. the maximum access time of 80 ns (t acc ) is guaranteed over the commercial temperature range (0c to +70c), 10% v cc supply voltage range (4.5v to 5.5v) and 100 pf output load.
28f002bc 2-mbit boot block flash memory e 6 preliminary pentium? processor 100/90 mhz cache main memory 82430fx pciset (82437fx) 82430fx pciset (82371fb) host bus pci bus isa bus x-bus 7 b 4 u s f 2 f 4 e 5 r x m e m r # x m e m w # pwrok vpp j1 xdir xoe# intel 28f002bc a[16:0] ce# oe# we# rp# dq[7:0] 0578_01 figure 1 . 28f002bc-t interface to a pentium? microprocessor system i pp , the maximum program current, is 20 ma. the v pp voltage for erase and program is 11.4v to 12.6v (v pp = 12v 5%) under all operating conditions. typical i cc active current is 20 ma. the 28f002bc flash memory is also designed with a standby mode to minimize system current drain and allow for low-power designs. when the ce# and rp# pins are at v cc , the cmos standby mode is enabled and i cc drops to about 50 a. a deep power-down mode is enabled when the rp# pin is at ground. in addition to minimizing power consumption, the deep power-down mode also provides write protection during power-up conditions. i cc current during deep power-down mode is 0.20 a typical. an initial maximum access time or reset time of 300 ns is required from rp# switching high until outputs are valid. equivalently, the device has a maximum wake-up time of 215 ns until writes to the cui are recognized. when rp# is at ground, the wsm is reset, the status register is cleared, and the entire device is write-protected. this feature prevents data corruption and protects the code stored in the device during system reset. the system reset pin can be tied to rp# to reset the memory to read mode at power-up. with on-chip program/erase automation and rp# functionality for data protection, the device is protected against unwanted program and/or erase cycles, even during system reset. 1.3 applications 2-mbit boot block flash memory combines high density, high performance, and cost-effective flash memory with blocking and hardware protection capabilities. its flexibility and versatility reduces cost throughout the product life cycle. flash memory is ideal for just-in-time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. during a products life cycle, flash memory reduces costs by allowing user- performed code updates and feature enhancements via floppy disk or remote link. the 28f002bc is a full-function blocked flash product suitable for a wide range of applications, including extended pc bios, digital cellular phone program and data storage, telecommunication boot/firmware, and various embedded applications where both program and data storage are required.
e 28f002bc 2-mbit boot block flash memory 7 preliminary reprogrammable systems, such as pers onal computers, are ideal applications for the 28f002bc. portable and hand-held personal computer applications are becoming more complex with the addition of power management software to take advantage of the latest microprocessor technology, the availability of rom-based application software, pen tablet code for electronic handwriting, and diagnostic code. figure 1 shows an example 28f002bc application. the increase in software sophistication augments the probability that a code update will be required after the pc is shipped. the 28f002bc provides a safe and inexpensive update solution for desktop, notebook, and hand-held personal computers while extending the product lifetime. furthermore, the deep power-down mode provides added flexibility for those battery-operated portable designs that require low power. the 28f002bc is also an excellent design solution for analog and digital cellular phone and telecommunication switching applications requiring high-performance, high-density storage in a small form factor package (x8-only bus). the blocking structure allows for easy segmentation of embedded code for modular software designs. for example, the parameter block can be used for frequently updated data storage and diagnostic messages (e.g., phone numbers and authorization codes). 1.4 pinouts the 28f002bc in the 44-lead psop pinout follows the industry-standard rom/eprom pinout, as shown in figure 4. the 2-mbit smartvoltage pinout, indicating the wp# input, is also shown in the same diagram. the 40-lead tsop package (shown in figure 2) offers the smallest form factor possible in addition to being compatible with its smartvoltage upgrade in the same package. the low-cost 40-lead pdip package diagram is shown in figure 3. e28f002bc boot block 40-lead tsop 10 mm x 20 mm top view 32 31 30 29 28 27 26 25 24 23 22 21 33 34 35 36 37 38 39 40 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 rp# we# v pp nc rp# we# v pp wp# nc nc 28f002bv 28f002bv a 12 a 16 a 15 a 14 a 13 a 11 a 9 a 8 a 8 a 9 a 11 a 12 a 13 a 14 a 15 a 16 a ce# oe# gnd gnd nc nc nc v cc v cc a 0 a 17 a 10 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 ce# oe# gnd gnd nc nc nc v cc v cc a 0 a 17 a 10 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 a 3 a 2 a 1 7 a 6 a 5 a 4 a a 3 a 2 a 1 7 a 6 a 5 a 4 0578_02 figure 2. the 40-lead tsop offers the smallest form factor for space-constrained applications
28f002bc 2-mbit boot block flash memory e 8 preliminary p28f002bc boot block 40-lead pdip 11 19 20 15 14 17 16 18 13 12 3 10 9 7 8 5 6 4 1 2 31 39 40 32 33 38 36 37 34 35 23 24 26 25 28 27 29 30 22 21 nc we# rp# nc nc gnd ce# gnd oe# nc nc a 0 dq 1 dq 2 dq 3 v cc dq 4 dq 5 dq 7 dq 6 a 10 a 17 dq 0 v cc 11 a a 12 a 13 a 14 a 16 8 a 9 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a v pp a 15 0578_3a figure 3. the 40-lead pdip offers the lowest cost package solution
e 28f002bc 2-mbit boot block flash memory 9 preliminary pa28f002bc boot block 44-lead psop 0.525" x 1.110" top view gnd we# rp# 32 31 30 29 27 26 25 24 23 33 34 35 36 37 38 39 40 41 42 43 44 ce# nc gnd oe# 22 21 20 19 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 nc nc nc nc nc v pp 28 17 28f200bv 28f200bv ce# wp# gnd oe# nc gnd we# rp# dq 7 a 0 dq 0 dq 1 dq 2 dq 3 dq 15 /a -1 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 a 7 a 6 a 5 a 4 a 2 a 3 a 1 a 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 -1 a dq 6 dq 5 dq 4 v cc v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 v pp dq 7 nc nc nc nc nc 0578_03 figure 4. the 44-lead psop offers a convenient upgrade from jedec rom standards
28f002bc 2-mbit boot block flash memory e 10 preliminary 1.5 pin descriptions table 1. 28f002bc pin descriptions symbol type name and function a C1 , a 0 Ca 17 input address inputs for memory addresses. addresses are internally latched during a write cycle. a -1 is used on the psop package only. a 17 is used on the tsop and pdip packages. a 9 input address input: when a 9 is at v hh, the signature mode is accessed. during this mode, a 0 decodes between the manufacturer and device ids. dq 0 C dq 7 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program operation. inputs commands to the command user interface when ce# and we# are active. data is internally latched during the write cycle. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. ce# input chip enable: activates the devices control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high deselects the memory device and reduces power consumption to standby levels. if ce# and rp# are high, but not at a cmos high level, the standby current will increase due to current flow through the ce# and rp# input stages. oe# input output enable: enables the devices outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command register and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse. rp# input reset/deep power-down: provides three-state control. puts the device in deep power-down mode, locks, and unlocks the boot block from program/erase. when rp# is at logic high level (6.5v maximum), the boot block is locked and cannot be programmed or erased. when rp# = v hh (11.4v minimum ), the boot block is unlocked and can be programmed or erased. when rp# is at a logic low level the boot block is locked, the deep power-down mode is enabled and the wsm is resetpreventing any blocks from being programmed or erased. when rp# transitions from logic low to logic high, the flash memory enters the read array mode. v cc device power supply: 5.0v 10%, 5.0v 5% v pp program/erase power supply: for erasing memory array blocks or programming data in each block. when v pp < v pplk all blocks are locked and memory contents cannot be altered. gnd ground: for all internal circuitry. nc no connect: pin may be driven or left floating.
e 28f002bc 2-mbit boot block flash memory 11 preliminary 2.0 product description output multiplexer status register identifier register data register write state machine command user interface i/o logic data comparator output buffer input buffer ce# we# oe# rp# program/erase voltage switch v v gnd pp cc y-gating/sensing 16-kbyte boot block 8-kbyte parameter block 8-kbyte parameter block 96-kbyte main block 128-kbyte main block y-decoder x-decoder input buffer address latch address counter power reduction control dq -dq 07 a -a 0 17 044819 figure 5. 28f002bc internal block diagram
28f002bc 2-mbit boot block flash memory e 12 preliminary 2.1 memory organization 2.1.1 blocking the 28f002bc features an asymmetrically-blocked architecture that provides system memory integration. each block can be erased up to 100,000 times. the block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. for the address locations of the blocks, see the memory map in figure 6. 2.1.1.1 boot block - 16 kb the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller- based system. the 16-kbyte (16, 384 bytes) boot block is located at the top of the address map as shown in figure 6. this boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental erasure. the boot block can be erased and written when rp# is held at 12v for the duration of the erase or program operation. this feature allows customers to change the boot code when necessary while providing security at other times. 28f002bc-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 00000h 1ffffh 20000h 37fffh 38000h 39fffh 3a000h 3bfffh 3c000h 3ffffh 0578_05 figure 6. 28f002bc-t memory map 2.1.1.2 parameter blocks - 8 kb (each) the 28f002bc has two 8-kbyte parameter blocks to facilitate storage of frequently updated system parameters that would normally require an eeprom. the parameter blocks can also be used to store additional boot or main code. by using software techniques, the byte-rewrite functionality of eeproms can be emulated. these techniques are detailed in intels application note ap-604 using intels boot block flash memory parameter blocks to replace eeprom. 2.1.1.3 main block - 96 kb and 128 kb the 28f002bc contains one 96-kbyte (98,304 byte) block and one 128-kbyte (131,072 byte) block. these blocks are typically used for data or code storage. 2.1.2 28f002bc-t block memory map the 16-kbyte boot block of the 28f002bc-t is located from 3c000h to 3ffffh. the first 8-kbyte parameter block resides in memory space from 3a000h to 3bfffh. the second 8-kbyte parameter block consumes the memory area from 38000h to 39fffh. the 96-kbyte main block extends from 20000h to 37fffh, while the 128-kbyte main block occupies the region from 00000h to 1ffffh. 3.0 principles of operation flash memory improves upon eprom capability with in-circuit electrical write and erase. the boot block flash memory utilizes a command user interface (cui) and automated algorithms to simplify write and erase operations. the cui allows for 100% ttl-level control inputs, fixed power supplies during erasure and programming, and maximum eprom compatibility. when v pp < v pplk , the device will only successfully execute the following commands: read array, read status register, clear status register, and intelligent identifier. the device provides standard eprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the cui or through the standard eprom a 9 high voltage (v id ) access for prom programming equipment. high voltage on v pp allows write and erase of the device. with v pp active, all functions associated
e 28f002bc 2-mbit boot block flash memory 13 preliminary with altering memory contents are accessible via the cui. the purpose of the write state machine (wsm) is to automate the write and erasure of the device completely. the wsm will begin operation upon receipt of a signal from the cui and will report status back through the status register. the cui will handle the we# interface to the data and address latches, as well as system software r equests for status while the wsm is in operation. 3.1 bus operations flash memory reads, erases and writes in- system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. these bus operations are summarized in tables 2 and 4. 3.2 read operations the 28f002bc has three user read modes: read array, read intelligent identifier, and read status register. during power-up conditions, it takes a maximum of 600 ns from when v cc is at 4.5v to when valid data is available at the outputs. 3.2.1 read array when rp# transitions from v il (reset) to v ih , the device will be in read array mode and will respond to the read control inputs (ce#, oe#, and address inputs) without any commands being written to the cui. when the device is in read array mode, four control signals must be manipulated to read data at the outputs. we# must be logic high (v ih ) ce# must be logic low (v il ) oe# must be logic low (v il ) rp# must be logic high (v ih ) in addition, the address of the desired location must be applied to the address pins. refer to ac characteristics for the exact sequence and timing of these signals. if the device is not in read array mode, as would be the case after a program or erase operation, the read mode command (ffh) must be written to the cui before array reads can take place. table 2. 28f002bc bus operations mode notes rp# ce# oe# we# a 9 a 0 v pp dq 0 C7 read 1,2,3 v ih v il v il v ih xxxd out output disable v ih v il v ih v ih x x x high z standby v ih v ih x x x x x high z deep power-down 8 v il x x x x x x high z intelligent identifier (mfr) 4 v ih v il v il v ih v id v il x 89h intelligent identifier (device) 4 v ih v il v il v ih v id v ih x 7ch write 5,6,7 v ih v il v ih v il xxv pph d in notes: 1. refer to dc characteristics. 2. x can be v il , v ih for control pins and addresses, v pplk or v pph for v pp . 3. see dc characteristics for v pplk , v pph , v hh , v id voltages. 4. manufacturer and device codes may also be accessed via a cui write sequence, a 1 -a 17 = x. 5. refer to table 3 for valid d in during a write operation. 6. command writes for program or block erase are only executed when v pp = v pph . 7. to write or erase the boot block, hold rp# at v hh . 8. rp# must be at gnd 0.2v to meet the maximum deep power-down current specified.
28f002bc 2-mbit boot block flash memory e 14 preliminary 3.2.2 intelligent identifiers the manufacturer and device codes are read via the cui or by taking the a 9 pin to v id . writing 90h to the cui places the device into intelligent identifier read mode. a read of location 00000h outputs the manufacturers identification code, 89h. reading location 00001h outputs the device id, 7ch. the 28f002bc device id of 7ch is identical to the e28f002bx (40-lead tsop). it differs from the pa28f200bx (44-lead psop), which has a device id of 2274h. designers using the pa28f200bx in the x8 mode who wish to migrate to the pa28f002bc need to be mindful of this device id difference and modify software drivers as necessary. the 40-lead pdip device id is 7ch. 3.3 write operations there are two commands that alter memory array contents: program setup and erase setup/confirm. in addition, the erase suspend command suspends the wsm during an erase operation and releases the cui to accept any read command (so long as it is to a block other than the one being erased). finally, there is a clear status register command for resetting the contents of the status register. this command should be invoked following all operations that modify the status register. all commands written to the cui will be interpreted, but for any write operation to be initiated, the v pp voltage must be at v hh . depending on the application, the design may have a switchable v pp power supply or the v pp may be hard-wired to 12v. the 28f002bc will function normally in either case. it is highly recommended that rp# is tied to the system reset for data protection during unstable cpu reset and also for proper cpu / flash synchronization. furthermore, when attempting to modify the contents of the 28f002bcs boot block area, v hh must be applied to both v pp and rp# for the operation to be valid. whether attempting to alter the contents of the boot block or any other memory array area, if the proper voltages are not applied to the correct input signals the write operation will be aborted. subsequently, the status register will respond with either bit 3 (v pp low error), bit 4 (program error) or bit 5 (erase error) being set (refer to table 5 for status register definitions). 3.3.1 command user interface (cui) the command user interface (cui) serves as the interface between the microprocessor and the internal chip controller. commands are written to the cui using standard microprocessor write timings. the available commands (summarized in tables 3 and 4) are read array, read intelligent identifier, read status register, clear status register, program setup, erase setup/confirm, and erase suspend. for read commands, the cui points the read path at either the array, the intelligent identifier, or the status register depending on the command received. for program or erase commands, the cui informs the write state machine (wsm) that a program or erase has been requested. during the execution of a program command, the wsm controls the programming sequences and the cui responds only to status register reads. during an erase cycle, the cui res ponds only to status register reads and erase suspend. after the wsm has completed its task, it will set the wsm status bit (bit 7 of the status register) to a 1, which will also allow the cui to respond to its full command set. note that after the wsm has returned control to the cui, the cui will stay in the read status register mode until it receives another command (see appendix b). table 3. command set codes and corresponding device mode command codes device mode 00 invalid/reserved 20 erase setup 40 program setup 50 clear status register 70 read status register 90 intelligent identifier b0 erase suspend d0 erase resume/erase confirm ff read array
e 28f002bc 2-mbit boot block flash memory 15 preliminary table 4. command bus definitions first bus cycle second bus cycle command notes oper addr data oper addr data read array write x ffh intelligent identifier 1,2 write x 90h read ia iid read status register write x 70h read x srd clear status register write x 50h program setup write pa 40h write pa pd block erase/confirm write ba 20h write ba d0h erase suspend/resume write x b0h write x d0h address data ba = block address srd = status register data ia = identifier address iid = intelligent identifier data pa = program address pd = program data x = don't care notes: 1. bus operations are defined in table 2. 2. following the intelligent identifier command, two read operations access manufacturer and device codes respectively. 3.3.1.1 command function description device operations are selected by writing specific commands into the cui. tables 3 and 4 define the available commands. status register (sr) bits are defined in table 5. invalid/reserved these are unassigned commands and should not be used. intel reserves the right to redefine these codes for future functions. read array (ffh) this single write cycle comm and points the read path at the array. if the host cpu performs a ce#/oe#-controlled read immediately following a two-write sequence (i.e., a program or erase command) that started the wsm, then the device will output status register contents. writing two read array (ffh) commands to the cui aborts the current operation and resets to read array mode. executing read array after the erase setup command (instead of giving erase confirm) causes the status register erase and program status bits to be set. this indicates that an erase operation was initiated but not successfully confirmed (an erase confirm at this point would be ignored by the cui). a subsequent read array command will point the data path at the array (see appendix b). intelligent identifier (90h) after this command is executed, the cui points the output path to the intelligent identifier circuits. only intelligent identifier values at addresses 0 and 1 can be read (only address a 0 is used in this mode; all other address inputs are ignored).
28f002bc 2-mbit boot block flash memory e 16 preliminary read status register (70h) this is one of three commands that is executable while the wsm is operating. after this command is written, a read of the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after program or erase has completed. clear status register (50h) the wsm can set the program status and erase status bits in the status register to 1, but it cannot clear them to 0. the status register is operated in this fashion for two reasons, the first is synchronization. since the wsm does not know when the host cpu has read the status register, it would not know when to clear the status bits. second, if the cpu is programming a string of bytes, it may be more efficient to query the status register after programming the string. thus, if any errors exist while programming the string, the status register will return the accumulated error status. the clear status register command clears the program, erase, and v pp status bits to 0. program setup (40h) this command simply sets the cui into a state such that the next write will load the address and data registers. after this command is executed, the outputs default to the status register. two consecutive read array commands (ffh) are required to reset to read array after the program setup command. program the write following the program setup command will latch address and data. also, the cui initiates the wsm to begin execution of the program algorithm. the device outputs status register data when oe# is enabled . to read array data after the program operation is completed, a read array command is required. erase setup (20h) the erase setup command prepares the cui for the erase confirm command. no other action is taken. if the next command is not an erase confirm command, then the cui will set both the program status and erase status bits of the status register to a 1, place the device into read status register mode, and wait for another command. erase confirm (d0h) if the previous command was an erase setup command, then the cui will enable the wsm to erase, at the same time closing the address and data latches, and respond only to the read status register and erase suspend commands. while the wsm is executing, the device will output status register data when oe# is toggled low. status register data can only be updated by toggling either oe# or ce#. if the previous command was not the erase setup command (20h), the erase confirm command is ignored. status register bits 4 and 5 are both set to indicate an invalid command sequence. erase suspend (b0h) this command is only valid while the wsm is executing an erase operation. at all other times, this command is ignored. after this command has been executed, the cui will set a signal that directs the wsm to suspend erase operations. while waiting for the erase to be suspended, the cui responds only to the read status register command or to the erase resume command. once the wsm has reached the suspend state, it will set an output in the cui that allows the cui to respond to the read array, read status register, and erase resume commands. in this mode, the cui will not respond to any other commands. the wsm will also set the wsm and erase suspend status bits to a 1. the wsm will continue to run, idling in the suspend state, regardless of the state of all input control pins except v pp and rp#. if v pp is taken below v pplk , the v pp low status bit (sr.3) will be set and the wsm will abort the suspended erase operation. if active, rp# will immediately shut down the wsm and the remainder of the chip. during a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path.
e 28f002bc 2-mbit boot block flash memory 17 preliminary erase resume (d0h) this command will cause the cui to clear the suspend state and clear the wsm status bit to a 0, but only if an erase suspend command was previously issued. erase resume will not have any effect under any other conditions. 3.3.2 status register the 28f002bc contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status register command to the cui. after writing this command, all subsequent read operations output data from the status register until another command is written to the cui. a read array command must be written to the cui to return to read array mode. the status register bits are output on dq[0:7]. the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs last in the read cycle. this prevents possible bus errors that might occur if the contents of the status register change while reading the status register. ce# or oe# must be toggled with each subsequent status read to insure the status register is updated; otherwise, the completion of a program or erase operation will not be evident from the status register. when the wsm is active, the status register will indicate the status of the wsm and upon command completion, it will indicate success or failure of the operation (see table 5 for definition of status register bits). 3.3.2.1 clearing the status register the wsm sets status bits 3 through 7 to 1, and clears bits 6 and 7 to 0, but cannot clear status bits 3 through 5 to 0. bits 3 through 5 can only be cleared by the controlling cpu through the use of the clear status register command. these bits can indicate various error conditions. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in s equence). the status register may then be read to determine if an error occurred during that programming or erasure series. this feature adds flexibility to the way the device may be programmed or erased. to clear the status register, the clear status register command is written to the cui. then, any other command may be issued to the cui. note, again, that before a read cycle can be initiated, a valid r ead command must be written to the cui to specify whether the read data is to come from the memory array, status register, or intelligent identifier. 3.3.3 program mode programming is executed using a two-write sequence. the program setup command is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm then executes a sequence of internally- timed events to: 1. program the desired bits of the addressed memory byte. 2. verify that the desired bits are sufficiently programmed. programming of the memory results in specific bits within a byte being changed to a 0. if the user attempts to program 1s, there will be no change in memory contents and no error is reported by the status register. similar to erasure, the status register indicates whether programming is complete. while the program sequence is executing, bit 7 of the status register is a 0. the status register can be polled by toggling either ce# or oe# to determine when the program sequence is complete. only the read status register command is valid while programming is active. when programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. if the programming operation was unsuccessful, bit 4 of the status register is set to a 1 to indicate a program failure. if bit 3 is set to a 1, then v pp was not within acceptable limits, and the wsm did not execute the programming sequence. if the program operation fails, bit 4 of the status register will be set within 1.5 ms, as determined by the timeout of the wsm. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, reads from the memory array cannot be accomplished until the cui is given the read array command. figure 7 shows the automated programming flowchart.
28f002bc 2-mbit boot block flash memory e 18 preliminary table 5. status register bit definition wsms ess es dws vpps r r r 76543210 notes: sr.7 = write state machine status (wsms) 1 = ready 0 = busy the write state machine bit must first be checked to determine program or block erase completion, before the program or erase status bits are checked for success. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, the wsm halts execution and sets both the wsms and ess bits to 1. the ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status 1 = error in block erasure 0 = successful block erase when this bit is set to 1, the wsm has applied the maximum number of erase pulses to the block and is still unable to successfully verify block erasure. sr.4 = program status 1 = error in byte program 0 = successful byte program when this bit is set to 1, the wsm has attempted but failed to program a byte. sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit, unlike an a/d converter, does not provide continuous indication of v pp level, but it does check the v pp level intermittently. the wsm interrogates v pp level only after the program or erase command sequences have been entered, and informs the system if v pp has not been switched on. if v pp ever goes below v pplk (even during an erase suspend) , the status register will set this bit and abort the operation in progress, even if v pp is returned to a valid level. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pph . sr.2Csr.0 = reserved for future enhancements these bits are reserved for future use and should be masked out when polling the status register. 3.3.4 erase mode erase setup and erase confirm commands to the cui, along with the address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. if the erase confirm command does not follow the erase setup command, the status register responds by setting both sr.4 and sr.5 to 1 to indicate an invalid command sequence. the wsm returns to read status register mode. the wsm then executes a sequence of internally timed events to: 1. program all bits within the block to 0. 2. verify that all bits within the block are sufficiently programmed to 0. 3. erase all bits within the block (set all bits to 1). 4. verify that all bits within the block are sufficiently erased. while the erase sequence is executing, bit 7 of the status register is a 0.
e 28f002bc 2-mbit boot block flash memory 19 preliminary when the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. if the erase operation was unsuccessful, bit 5 of the status register will be set (within 1.5 ms) to 1, indicating an erase failure. if v pp is not within acceptable during the suspended period, the wsm does not execute the erase sequence; instead, bit 5 of the status register is set to a 1 to indicate an erase failure, and bit 3 is set to a 1 to indicate that the v pp supply voltage was outside acceptable limits. the status register should be cleared before attempting the next operation. any cui instruction can follow after erasure is completed; however, reads from the memory array cannot be accomplished until the cui is given the read array command. figure 8 details the automated block erase flowchart. 3.3.4.1 suspending and resuming erase since an erase operation may take a few seconds to complete, an erase suspend command is provided. this allows erase-sequence interruption in order to read data from another block of the memory array. once the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pause the erase sequence at a predetermined point in the erase algorithm. the status register must then be read to determine if the erase operation has been suspended. taking v pp below v pplk latches the v pp low status and aborts the operation in progress. v pp should be main- tained at valid levels, even during erase suspend. at this point, a read array command can be written to the cui in order to read data from blo cks other than that being erased. the only other valid commands at this time are erase resume and read status register. during erase suspend mode, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. to resume the erase operation, the chip must be enabled by taking ce# to v il , then issuing the erase resume command. when the erase resume command is given, the wsm will continue with the erase sequence and finish erasing the block. as with the end of a standard erase operation, the status register must be read, cleared, and the next instruction issued in order to continue. figure 9 highlights the erase suspend/resume flowchart. 3.3.5 extended cycling intel has designed extended cycling capability into its etox iv flash memory technology. the 28f002bc flash memory is designed for 100,000 program/erase cycles on each of the five blocks. at 10% v pp , the parameter blocks are c apable of 10,000 program/erase cycles. the combination of low electric fields, clean oxide processing and minimized oxide area per memory cell subjected to the tunneling electric field results in very high cycling capability. 3.4 boot block locking the boot block memory architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blo cks are programmed and erased independently as necessary. only the boot block can be locked independently from the other blocks. 3.4.1 v pp = v il for complete protection for complete write protection of all blocks in the flash device, the v pp programming voltage can be held low. when v pp is below v pplk , any program or erase operation will cause the device to set an error bit in the status register. 3.4.2 rp# = v hh for boot block unlocking in the case of boot block modifications (write and erase), rp# and v pp are set to v hh (12v). however, if rp# is not at v hh when a program or erase operation of the boot block is attempted, the corresponding status register bit (bit 4 for program and bit 5 for erase, refer to table 5 for status register definitions) is set to indicate the failure to complete the specified operation.
28f002bc 2-mbit boot block flash memory e 20 preliminary sr.7 = 1 ? no yes start write 40h and byte address full status check if desired program complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v range error pp bus operation command comments standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write program setup data = data to program addr = location to program read data = 40h addr = byte to program check sr.7 1 = wsm ready 0 = wsm busy standby sr.3 = sr.4 = program error program successful check sr.4 1 = program error check sr.3 1 = v low detect pp program status register data toggle ce# or oe# to update srd. write data and data address repeat for subsequent writes. sr full status check can be done after each write, or after a sequence of writes. write ffh after the last write operation to reset device to read array mode. 0578_06 figure 7. automated programming flowchart
e 28f002bc 2-mbit boot block flash memory 21 preliminary sr.7 = 0 1 start write 20h and block address write d0h and block address full status check if desired block erase complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v range error suspend erase suspend erase loop yes no 1 0 command sequence error sr.3 = sr.5 = sr.4,5 = block erase error pp bus operation command comments standby check sr.4,5 both 1 = command sequence error standby sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erase before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1 = block erase error standby bus operation command comments write write erase setup read data = 20h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to reset device to read array mode. status register data toggle ce# or oe# to update status register standby erase confirm data = d0h addr = within block to be erased block erase successful check sr.3 1 = v low detect pp 0578_07 figure 8. automated block erase flowchart
28f002bc 2-mbit boot block flash memory e 22 preliminary sr.7 = 0 1 start write b0h read status register write d0h erase resumed bus operation command comments write erase suspend read data = b0h addr = x check sr.7 1 = wsm ready 0 = wsm busy status register data toggle ce# or oe# to update srd. addr = x standby sr.6 = write ffh read array data done reading erase completed write ffh read array data yes no 0 1 check sr.6 1 = erase suspended 0 = erase completed standby data = ffh addr = x write read array data from block other than the one being erased read data = d0h addr = x write read array erase resume 0578_08 figure 9. erase suspend/resume flowchart
e 28f002bc 2-mbit boot block flash memory 23 preliminary 3.5 power consumption 3.5.1 active power with ce# at a logic-low level and rp# at a logic- high level, the device is placed in the active mode. the device i cc current is a maximum of 60 ma at 10 mhz with ttl input signals. 3.5.2 standby power with ce# at a logic-high level (v ih ), the memory is placed in standby mode, where the maximum i cc standby current is 100 m a. the standby operation disables much of the devices circuitry and substantially reduces device power consumption. the outputs (dq[0:7]) are placed in a high- impedance state independent of the status of the oe# signal. when ce# is at a logic-high level during erase or program, the device will continue to perform the erase or program function and consume erase or program active power until erase or program is completed. 3.5.3 deep power-down the 28f002bc flash memory supports a typical i cc of 0.2 m a in deep power-down mode. this mode is activated by the rp# pin when it is at a logic-low (gnd 0.2v); in this mode, all internal circuits are turned off to save power. setting the rp# pin low de-selects the memory and places the output drivers in a high impedance state. recovery from the deep power-down state requires a minimum access time of 300 ns (see ac characteristics table, t phqv parameter). during erase or program modes, rp# low will abort either erase or program operations, but the memory contents are no longer valid as the data has been corrupted. rp# transitions to v il or turning power off to the device will clear the status register. 3.6 power-up/down operation the 28f002bc offers protection against accidental block erasure or programming during power transitions. power supply sequencing is not required , since the device is indifferent as to which power supply, v pp or v cc , powers-up first. the cui is reset to the read mode after power-up, but the system must drop ce# low or present a new address to ensure valid data at the outputs. a system desi gner must guard against spurious writes when v cc voltages are above v lko and v pp = v hh . since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powerg ood/reset) during power up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.1 rp# connected to system reset the use of rp# during system reset is important with automated write/erase devices because the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization would not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper cpu initialization following a system reset by connecting the rp# pin to the same reset# signal that resets the system cpu. 3.6.2 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp , ce# transitions, or wsm actions. its default state upon power-up, after exit from deep power-down mode, or after v cc transitions above v lko , is read array mode. after any program or block erase operation is complete, and even after v pp transitions down to v pplk , the cui must be reset to read array mode via the read array command if access to the flash memory is desired.
28f002bc 2-mbit boot block flash memory e 24 preliminary 3.7 power supply decoupling flash memorys power switching characteristics require careful device decoupling methods. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. active current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce# transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 v pp trace on printed circuit boards designing for in-system writes to the flash memory requires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. one should use similar trace widths and layout considerations given to the v cc power supply trace. adequate v pp supply traces and decoupling capacitors placed adjacent to the component will decrease spikes and overshoots.
e 28f002bc 2-mbit boot block flash memory 25 preliminary 4.0 electrical specifications 4.1 absolute maximum ratings operating temperature during read ................................ 0c to +70c during write and block erase...... 0c to +70c temperature bias .................... C10c to +80c storage temperature................... C65c to +125c voltage on any pin (except v cc , v pp , a 9 and rp#) with respect to gnd ............. C2.0v to +7.0v (1) voltage on pin rp# or pin a 9 with respect to gnd ........ C2.0v to +13.5v (1, 2) v pp program voltage with respect to gnd during write and block erase .............. C2.0v to +14.0v (1, 2) v cc supply voltage with respect to gnd ............ C2.0v to +7.0v (1) output short circuit current.....................100 ma (3) notice: this datasheet contains preliminary information on new products in production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0v for periods <20 ns. maximum dc voltage on rp# or a 9 may overshoot to 13.5v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4.2 operating conditions table 6. temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature 0 70 c v cc 5v v cc supply voltage (10%) 4.50 5.50 volts
28f002bc 2-mbit boot block flash memory e 26 preliminary 4.2.1 capacitance t a = +25 c, f = 1 mhz symbol parameter notes typ max unit conditions c in input capacitance 1 6 8 pf v in = 0v c out output capacitance 1, 2 10 12 pf v out = 0v notes: 1. sampled, not 100% tested. 2. for the 28f002bc, address pin a 10 follows the c out capacitance numbers. 4.2.2 input/output test conditions test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0578_09 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic 1 and v ol (0.45 v ttl ) for a logic 0. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . figure 10. inputs and measurement points out device under test 1.3v r l 1n914 c l 0578_10 notes: c l = 100 pf, includes jig capacitance r l = 3.3k w figure 11. standard test configuration
e 28f002bc 2-mbit boot block flash memory 27 preliminary 4.2.3 dc characteristics table 7. dc characteristics symbol parameter notes min typ max units test conditions i il input load current 1 1.0 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3 1.5 ma v cc = v cc max ce# = rp# = wp# = v ih 50 100 a v cc = v cc max ce# = rp# = v cc 0.2v i ccd v cc deep power-down current 1 0.2 8.0 a v cc = v cc max v in = v cc or gnd rp# = gnd 0.2v i ccr v cc read current 1,5 20 55 ma cmos inputs v cc = v cc max ce# = gnd f = 10 mhz i out = 0 ma cmos inputs: gnd 0.2v or v cc 0.2v 20 60 ma ttl inputs v cc = v cc max ce# = v il f = 10 mhz i out = 0 ma ttl inputs: v il or v ih i ccw v cc program current 1,4 50 ma byte prog. in progress i cce v cc erase current 1,4 30 ma block erase in progress i cces v cc erase suspend current 1,2 5 10 ma ce# = v ih block erase suspend i pps v pp standby current 1 10 a v pp v cc i ppd v pp deep power-down current 1 5.0 a rp# = gnd 0.2v i ppr v pp read current 1 200 a v pp > v cc i ppw v pp program current 1,4 20 ma v pp = v pph byte prog. in progress i ppe v pp erase current 1,4 15 ma v pp = v pph block erase in progress i ppes v pp erase suspend current 1 200 a v pp = v pph block erase suspended
28f002bc 2-mbit boot block flash memory e 28 preliminary table 7. dc characteristics (continued) symbol parameter notes min typ max units test conditions i rp# rp# boot block unlock current 1,4 500 a rp# = v hh i id a 9 intelligent identifier current 1,4 500 a a 9 = v id v id a 9 intelligent identifier voltage 10.8 13.2 v v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5v v v ol output low voltage 0.45 v v cc = v cc min i ol = 5.8 ma v oh output high voltage (ttl) 2.4 v v cc = v cc min i oh = C2.5 ma output high voltage (cmos) 0.85 v cc v v cc = v cc min i oh = C1.5 ma v cc C 0.4v v cc = v cc min i oh = C100 m a v pplk v pp lock-out voltage 3 0.0 6.5 v complete write protection v pph v pp (program/ erase operations) 7 11.4 12.0 12.6 v v pph v pp (program/ erase operations) 8 10.8 12.0 13.2 v v lko v cc erase/write lock voltage 2.0 v v hh rp# unlock voltage 8 10.8 12.0 13.2 v boot block unlock voltage notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, v pp =12.0v , t = +25c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and byte writes are inhibited when v pp = v pplk , and not guaranteed in the range between v pph and v pplk . 4. sampled, not 100% tested. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. v cc = 12.0v 10% for applications requiring 100,000 block erase cycles. 7. v pp = 12.0v 5% for applications requiring 100,000 block erase cycles. 8. v pp = 12.0v 10% for applications requiring wider v pp tolerances: parameter blocks can sustain 10,000 block erase cycles; main blocks support up to 100 block erase cycles. note that erase times are close to maximum spec limits when using this option.
e 28f002bc 2-mbit boot block flash memory 29 preliminary 4.2.4 ac characteristics table 8. ac characteristics: read only operations 28f002bc-80 28f002bc-120 symbol parameter notes v cc = 5v 10% 100 pf v cc = 5v 10% 100 pf units min max min max t avav read cycle time 80 120 ns t avqv address to output delay 80 120 ns t elqv ce# to output delay 2 80 120 ns t phqv rp# to output delay 300 300 ns t glqv oe# to output delay 2 40 40 ns t elqx ce# to output in low z 3 0 0 ns t ehqz ce# to output in high z 3 30 30 ns t glqx oe# to output in low z 3 0 0 ns t ghqz oe# to output in high z 3 30 30 ns t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce t oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. see standard test configuration (figure 11).
28f002bc 2-mbit boot block flash memory e 30 preliminary address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v phqv t high z valid output data valid standby avav t ehqz t ghqz t oh t glqv t glqx t elqv t elqx t avqv t high z 0578_11 figure 12. ac waveforms for read operations table 9. ac characteristics: we# controlled write operations (1) 28f002bc-80 28f002bc-120 symbol parameter notes v cc = 5v 10% 100 pf v cc = 5v 10% 100 pf units min max min max t avav write cycle time 80 120 ns t phwl rp# setup to we# going low 215 215 ns t elwl ce# setup to we# going low 0 0 ns t phhwh boot block lock setup to we# going high 6, 8 100 100 ns t vpwh v pp setup to we# going high 5, 8 100 100 ns t avwh address setup to we# going high 3 50 50 ns t dvwh data setup to we# going high 4 50 50 ns t wlwh we# pulse width 50 50 ns t whdx data hold time from we# high 4 0 0 ns t whax address hold time from we# high 3 0 0 ns t wheh ce# hold time from we# high 0 0 ns
e 28f002bc 2-mbit boot block flash memory 31 preliminary table 9. ac characteristics: we# controlled write operations (1) (continued) 28f002bc-80 28f002bc-120 symbol parameter notes v cc = 5v 10% 100 pf v cc = 5v 10% 100 pf units min max min max t whwl we# pulse width high 20 20 ns t whqv1 duration of programming operation 2, 5 6 6 s t whqv2 duration of erase operation (boot) 2, 5, 6 0.3 0.3 s t whqv3 duration of erase operation (parameter) 2,5 0.3 0.3 s t whqv4 duration of erase operation (main) 2, 5 0.6 0.6 s t qvvl v pp hold from valid srd 5, 8 0 0 ns t qvph rp# v hh hold from valid srd 6, 8 0 0 ns t phbr boot block lock delay 7, 8 100 100 ns notes: 1. read timing characteristics during write and erase operations are the same as during read-only operations. refer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. refer to command definition table for valid a in . 4. refer to command definition table for valid d in . 5. program/erase durations are measured to valid srd data (successful operation, sr.7 = 1). 6. for boot block program/erase, rp# should be held at v hh until operation completes successfully. 7. time t phbr is required for successful relocking of the boot block. 8. sampled, but not 100% tested.
28f002bc 2-mbit boot block flash memory e 32 preliminary addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v il v in d in a in a avav t avwh t whax t in d wheh t whwl t valid srd in d whqv1,2,3,4 t vpwh t qvvl t qvph t phhwh t ih v phwl t high z whdx t dvwh t wlwh t ih v il v v (v) pp 12 3 4 6 5 pph v pplk v pph v1 2 wp# il v ih v elwl t 0578_12 notes: 1. v cc power-up and standby 2. write program setup or erase setup command 3. write valid address and data (program or erase confirm command 4. automated program or erase delay 5. read status register data 6. write read array command figure 13. ac waveforms for write and erase operations (we# controlled writes)
e 28f002bc 2-mbit boot block flash memory 33 preliminary table 10. ac characteristics: ce# controlled write operations (1,9) 28f002bc-80 28f002bc-120 symbol parameter notes v cc = 5v 10% 100 pf v cc = 5v 10% 100 pf units min max min max t avav write cycle time 80 120 ns t phel rp# high recovery to ce# going low 215 215 ns t wlel we# setup to ce# going low 0 0 ns t phheh boot block lock setup to ce# going high 6, 8 100 100 ns t vpeh v pp setup to ce# going high 5, 8 100 100 ns t aveh address setup to ce# going high 3 50 50 ns t dveh data setup to ce# going high 4 50 50 ns t eleh ce# pulse width 50 50 ns t ehdx data hold time from ce# high 4 0 0 ns t ehax address hold time from ce# high 3 0 0 ns t ehwh we # hold time from ce# high 0 0 ns t ehel ce# pulse width high 30 30 ns t ehqv1 duration of programming operation 2, 5 6 6 s t ehqv2 duration of erase operation (boot) 2, 5, 6 0.3 0.3 s t ehqv3 duration of erase operation (parameter) 2, 5 0.3 0.3 s t ehqv4 duration of erase operation (main) 2, 5 0.6 0.6 s t qvvl v pp hold from valid srd 5, 8 0 0 ns t qvph rp# v hh hold from valid srd 6, 8 0 0 ns t phbr boot block lock delay 7, 8 100 100 ns notes: see we# controlled write operations for notes 1 through 8. 9. chip-enable controlled writes: write operations are driven by the valid combination of ce# and we# in systems where ce# defines the write pulse-width (within a longer we# timing waveform), all set-up, hold and inactive we# times should be measured relative to the ce# waveform.
28f002bc 2-mbit boot block flash memory e 34 preliminary addresses (a) we# (e) oe# (g) ce# (w) data (d/q) rp# (p) ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v in d in a in a avav t in d valid srd in d qvph t phheh t high z ehdx t ih v il v v (v) pp 12 3 4 6 5 ehax t ehqv1,2,3,4 t ehel t ehwh t eleh t dveh t vpeh t qvvl t phwl t wlel t aveh t pplk v pph v1 2 pph v il v ih v il v ih v wp# 0578_13 notes: 1. v cc power-up and standby 2. write program setup or erase setup command 3. write valid address and data (program or erase confirm command 4. automated program or erase delay 5. read status register data 6. write read array command figure 14. alternate ac waveforms for write and erase operations (ce# controlled writes) table 11. erase and program timings (t a = +25c) v pp = 12v 10% 2 v pp = 12v 5% parameter 1 v cc = 5v 10% v cc = 5v 10% units typ max typ max boot/parameter block erase time 5.8 40 1.0 7 s main block erase time 14 60 2.4 14 s main block write time 6.0 20 1.2 4.2 s notes: 1. all numbers are sampled, not 100% tested. 2. erase times near max limits when the 10% v pp option is used.
e 28f002bc 2-mbit boot block flash memory 35 preliminary appendix a ordering information e28f00 b 2 c- t1 0 2 package e = 40-lead tsop p = 40-lead pdip pa = 44-lead psop product line designator for all intel flash products density/organization 00x = x8-only (x = 2) access speed (ns) 80, 120 t = top boot architecture b = boot block 0578_14 valid combinations: 40-lead tsop 40-lead pdip 44-lead psop commercial 2 m e28f002bc-t80 p28f002bc-t80 pa28f002bc-t80 e28f002bc-t120 P28F002BC-T120 pa28f002bc-t120
28f002bc 2-mbit boot block flash memory e 36 preliminary appendix b wsm transition table write state machine current/next states command input (and next state) current state sr.7 data when read read array (ffh) program setup (40h) erase setup (20h) erase confirm (d0h) erase susp. (b0h) erase resume (d0h) read status (70h) clear status (50h) read id (90h) read array 1 array read array program setup erase setup read array read status read array read id program setup 1 status program (command input = byte program data) program * (not comp.) 0 status program program (comp.) 1 status read array program setup erase setup read array read status read array read id erase setup 1 status erase command error erase erase cmd. error erase erase command error erase cmd. error 1 status read array program setup erase setup read array read status read array read id erase (not comp.) 0 status erase erase susp. to status erase erase (comp.) 1 status read array program setup erase setup read array read status read array read id erase suspend to status 1 status erase susp. to array erase susp. to array erase susp. to array erase erase susp. to array erase erase susp. to status erase susp. to array erase susp. to array erase suspend to array 1 array erase susp. to array erase susp. to array erase susp. to array erase erase susp. to array erase erase susp. to status erase susp. to array erase susp. to array read status 1 status read array program setup erase setup read array read status read array read id read identifier 1 id read array program setup erase setup read array read status read array read id note: you cannot program 1s to the flash. writing ffh after the program setup command will initiate the program algorithm of the wsm machine. the wsm will attempt the program, realize you are trying to program 1s, and exit to read status mode without changing memory contents. no error is returned. writing another ffh while in read status mode will return the flash to read array.
e 28f002bc 2-mbit boot block flash memory 37 preliminary appendix c additional information related intel information (1,2) order number document 292130 ab-57 boot block architecture for safe firmware updates 292098 ap-363 extended flash bios concepts for portable computers 292148 ap-604 using intels boot block flash memory parameter blocks to replace eeprom 292161 ap-608 implementing a plug and play bios using intels boot block flash memory 292163 ap-610 flash memory in-system code and data update techniques 290448 28f002/200bx-t/b 2-mbit boot block flash memory datasheet 290451 28f004/400bx-t/b 4-mbit boot block flash memory datasheet 290531 28f002/200bv-t/b 2-mbit smartvoltage flash memory datasheet 290530 28f004/400bv-t/b 4-mbit smartvoltage flash memory datasheet notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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